1. Technical Field
The present invention relates to a nonvolatile semiconductor memory device which is capable of improving performance of memory cells and reducing leakage current by using high dielectric materials for an inter-electrode insulating film in a stack gate structure having a floating gate electrode, and a method of manufacturing the same.
2. Description of Related Art
An NAND flash memory (one of nonvolatile semiconductor memory devices) will be hereinafter described by way of an example.
A memory cell of an NAND volatile semiconductor memory device has a stack structure in which a tunneling insulating film and a floating gate electrode are formed on a semiconductor substrate and a control gate electrode is formed on the floating gate electrode via an inter-electrode insulating film. In such a memory cell, shift of a threshold voltage, generated by electron injection into the floating gate electrode from a silicon substrate with applying a high electric field to the tunneling insulating film, is used for storage of information. It is desirable that the inter-electrode insulating film has high coupling ratio with high capacitance, and small leakage current.
A method of manufacturing a memory cell of a conventional NAND nonvolatile semiconductor memory device will be described below with reference to FIGS. 6A to 8. Figures in the left and right sides of each of FIGS. 6A to 8 show cross sections perpendicular to each other.
First, an about 7˜8 nm thick silicon oxide film 102, which is formed by thermal oxidation as a tunneling insulating film, is formed on a silicon substrate 101 doped with a predetermined impurity, and then, a 60 nm thick phosphorus-doped polycrystalline silicon layer 103 as a floating gate electrode and a mask material 104 for device isolation are sequentially deposited on the silicon oxide film 102 by a chemical vapor deposition (CVD) method. Thereafter, the mask material 104, the polycrystalline silicon layer 103 and the tunneling insulating film 102 are sequentially etched by a reactive ion etching (RIE) method using a resist mask (not shown), and an exposed region of the silicon substrate 101 is etched to form a trench 106 having a depth of 100 nm (FIG. 6A).
Next, a silicon oxide film 107 for device isolation is deposited on the entire surface to fill the trench 106, and then, the silicon oxide film 107 is removed from the surface by a chemical mechanical polishing (CMP) method to planarize the surface, thereby exposing the mask material 104 (FIG. 6B).
After the exposed mask material 104 is selectively etched away, an exposed surface of the silicon oxide film 107 is etched away with a dilute hydrofluoric acid solution and a side wall 108 of the polycrystalline silicon layer 103 is exposed. Then, a SiO2/SiN/SiO2 film (hereinafter abbreviated as an ONO film) 109 as an inter-electrode insulating film, which has a stack structure of silicon oxide and silicon nitride, is deposited on the entire surface. The equivalent SiO2 thickness of the ONO film is 15 nm or so. At this time, the inter-electrode insulating film 109 is formed on both of the surface and the side wall 108 of the polycrystalline silicon layer 103 three-dimensionaly (FIG. 7A). Since an average dielectric constant of the ONO film 109 is as low as 5 or so, it is necessary to increase effective capacitance by forming the inter-electrode insulating film 109 three-dimensionaly to increase a contact area between the inter-electrode insulating film 109 and the polycrystalline silicon layer 103.
Subsequently, a 100 nm thick conductive layer 110 made of a polycrystalline silicon layer as a control gate electrode is deposited by a CVD method, and then, a mask material 111 for RIE is deposited by a CVD method. Thereafter, the mask material 111, the conductive layer 110, the inter-electrode insulating film 109, the polycrystalline silicon layer 103, and the tunneling insulating film 102 are sequentially etched by RIE using a resist mask (not shown) to form slit regions 112 in a word line direction (FIG. 7B). Thus, shapes of the polycrystalline silicon layer 103 as the floating gate electrode and the conductive layer 110 as the control gate electrode are determined.
Finally, a silicon oxide film 113 is formed on the exposed surface and the electrode side walls by thermal oxidation, and a source and drain regions 114 are formed by an ion implantation method, and then, an inter-layer insulating film 115 is formed by a CVD method to cover the entire surface (FIG. 8). Thereafter, wiring layers and so on are formed by a method known in the related-art to complete the memory cell.
In the above-constructed memory cell of the NAND nonvolatile semiconductor memory device, leakage current flows in the inter-electrode insulating film 109 to the control gate electrode when a high electric field is applied to the inter-electrode insulating film 109 during writing and erasing operations. Since the leakage current obstructs charge storing and erasing in the floating gate electrode via the tunneling insulating film, it is necessary to keep the leakage current lower than the device specification level.
According to wide investigations, it is proved that the leakage current must be less than 1/10 of the current flow into the tunneling insulating film, just before a writing operation is completed. For example, by assuming that the thickness of the tunneling insulating film is 7.5 nm, a coupling ratio between the tunneling insulating film and the inter-electrode insulating film is 0.6, and the inter-electrode insulating film has a three-dimensional structure, an effective electric field (defined by ‘surface charge density/SiO2 dielectric constant’) applied to the inter-electrode insulating film is estimated to be 12˜18 MV/cm or so.
In that case, an acceptable leakage current density in the inter-electrode insulating film is about 1×10−2 A/cm2.
In order to obtain higher storage capacity of the NAND nonvolatile semiconductor memory device, it is required that the memory device should contain more memory cells, each having miniaturized gate length and gate width. To miniaturize the memory cell, there have been proposed that higher dielectric constant materials (high-k materials) are used for an inter-electrode insulating film, instead of the ONO film that has been conventionally used (see JP-A-11-297867, for example), the reasons for which are as follows.
One of the reasons is that distance between memory cells becomes much smaller in the 50 nm technology node, the inter-electrode insulating film can not be formed three-dimensionaly on the side wall of the floating gate electrode 108, as shown in FIG. 7A.
The miniaturized memory cell should have a so-called plainer cell structure in which the inter-electrode insulating film is formed only on the surface, not on the side walls of the floating gate electrode. The plainer cell structure needs a material having a dielectric constant higher than that of the conventional ONO film. This is because a material having a high dielectric constant can provide high capacitance even if the inter-electrode insulating film is formed in plainer, not in three-dimensionaly.
Another reason is that the plainer cell structure might be applied an effective electric field of about 30 MV/cm to the inter-electrode insulating film, which is twice as high as that of a three-dimensional cell structure. According to a device specification, it is necessary to keep leakage current density in the inter-electrode insulating film lower than 1×10−2 A/cm2 even with such a high electric field. The related-art ONO film can not be used as the inter-electrode insulating film in the plainer cell structure since the leakage current suddenly increases in the high electric field. From this standpoint, high-k materials having dielectric constants higher than that of the ONO film should be used as the inter-electrode film. They can suppress the leakage current even with the high electric field by increasing a physical thickness, while the equivalent SiO2 thickness is not increased so much due their high dielectric constants.
Rare-earth oxide, rare-earth nitride and rare-earth oxynitride, etc., which include rare-earth elements, are potential candidates for high-k materials. Since these materials generally have a high electron barrier as well as a high dielectric constant (high-k), it is highly expected that they can be practically used as the inter-electrode insulating film in the plainer cell structure. However, these materials have their inherent problem in the conventional manufacturing method as described below.
As shown in FIGS. 7A and 8, after forming the inter-electrode insulating film, thermal treatment is required to form the control gate electrode and an electrode side wall oxide film. In addition, a thermal treatment is required to activate impurities in the source and drain diffusion regions formed by ion implantation. For example, a rapid thermal treatment is performed for 30 seconds in a temperature range of 900˜1000° C. to activate impurities in the source and drain diffusion regions.
FIG. 9 shows change of a LaAlO3 (rare-earth oxide) film structure deposited on silicon substrate after rapid thermal treatment is performed for 30 seconds at the temperature of 900° C. under a nitrogen atmosphere. This condition corresponds to thermal treatment for impurity activation of the source and drain diffusion regions. As can be seen from the right figure of FIG. 9, it is apparent that Si is diffused from the silicon substrate into the LaAlO3 by thermal treatment, LaAlO3 is changed into La silicate containing Al, and the physical thickness of the film rapidly increases. This is because that a metal oxynitride including a rare-earth element such as La is highly reactive with Si.
Accordingly, the dielectric constant of the inter-electrode insulating film formed on the floating gate electrode made of a Si containing conductive material such as polycrystalline silicon decreases with increasing the physical thickness due to large Si diffusion by the above-mentioned rapid thermal treatment, which is required in a device manufacturing process, resulting in large capacitance decrease of the inter-electrode insulating film.
Such deterioration of the inter-electrode insulating film raises a problem of insufficient performance in writing, eraseing, reading, and data retaining of the memory cell. In addition, as the dielectric constant decreases, breakdown voltage decreases to 20 MV/cm or so while the leakage current density increases up to 1×10−2 A/cm2, which do not satisfy the device specification.
As shown in FIG. 10, in order to suppress such Si diffusion, it may be considered to form barrier layers made of SiN or Al2O3 between a floating gate electrode and an inter-electrode insulating film. Since SiN or Al2O3 has a dielectric constant lower than that of metal oxynitride including rare-earth elements, effective capacitance of the inter-electrode insulating film is reduced, resulting in deteriorating performance of the memory cell.
As described above, there is a serious problem that Si in the silicon substrates or polycrystalline silicon adjacent to the inter-electrode insulating film diffuses in large quantities into the inter-electrode insulating film, which is made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, by thermal treatment. In particulary, the problem is the large quantities of Si diffusion and its uncontrollability.
As rare-earth oxide, rare-earth nitride or rare-earth oxynitride including rare-earth elements with high dielectric constants is used as the inter-electrode insulating film in the memory cell with the floating gate electrode, quality of the inter-electrode insulating film is deteriorated due to the thermal treatment after deposition of the inter-electrode insulating film. Therefore, the dielectric constant is decreased, resulting in deterioration in leakage current characteristics. Accordingly, such a memory device can not achieve high-performances in writing, erasing, reading, and data retaining of the memory cell.